The actual mapping to a physical address is a function of the paging mechanism and is invisible to the programmer. In a virtual memory system, the effective address is a virtual address or a register. In a system without virtual memory, the effective address will be either a main memory address or a register. What is the interpretation of effective address. The value of the mode field determines which addressing mode is to be used. Also, one or more bits in the instruction format can be used as a mode field. Opcodes will use different addressing modes. The question arises as to how the control unit can determine which addressing mode is being used in a particular instruction.
PC holds the address of the instruction to be executed next and in incremented each time an instruction is fetched from memory.Īddressing Modes: The most common addressing techniques are
Program Counter (PC) keeps track of the instruction in the program stored in memory. The basic operation cycle of the computer (1) (2) (3)įetch the instruction from memory Decode the instruction Execute the instruction (2) To reduce the number of bits in the addressing fields of the instruction. (1) To give programming versatility to the uses by providing such facilities as pointer to memory, counters for top control, indexing of data, and program relocation. Computer use addressing mode technique for the purpose of accommodating one or both of the following provisions. The addressing mode specifies a rule for interpreting or modifying the address field of the instruction between the operand is activity referenced. The way the operands are chosen during program execution is dependent on the addressing mode of the instruction. This operation must be executed on some data stored in computer register as memory words. Jordan, “Computer Systems Design and Architecture”, Second Edition, Pearson Education, 2004.Computer Organization and Architecture Addressing mode Introduction About Addressing mode:Addressing Modes The operation field of an instruction specifies the operation to be performed. Hayes, “Computer Architecture and Organization”, Third Edition, Tata McGraw Hill, 1998. William Stallings, “Computer Organization and Architecture – Designing for Performance”, Sixth Edition, Pearson Education, 2003. Hardware/Software interface”, Third Edition, Elsevier, 2005.
Hennessy, “Computer Organization and Design: The Carl Hamacher, Zvonko Vranesic and Safwat Zaky, “Computer Organization”, Fifth Edition, Tata McGraw Hill, 2002. UNIT V I/O ORGANIZATIONĪccessing I/O devices – Programmed Input/Output -Interrupts – Direct Memory Access – Buses – Interface circuits – Standard I/O Interfaces (PCI, SCSI, USB), I/O devices and processors. UNIT IV MEMORY SYSTEM 9 Basic concepts – Semiconductor RAM – ROM – Speed – Size and cost – Cache memories – Improving cache performance – Virtual memory – Memory management requirements – Associative memories – Secondary storage devices. UNIT III PIPELINING 9 Basic concepts – Data hazards – Instruction hazards – Influence on instruction sets – Data path and control considerations – Performance considerations – Exception handling. UNIT II BASIC PROCESSING UNITįundamental concepts – Execution of a complete instruction – Multiple bus organization – Hardwired control – Micro programmed control – Nano programming. ALU design – Fixed point and floating point operations.
UNIT I BASIC STRUCTURE OF COMPUTERS 9 Functional units – Basic operational concepts – Bus structures – Performance and metrics – Instructions and instruction sequencing – Hardware – Software Interface – Instruction set architecture – Addressing modes – RISC – CISC. COMPUTER ORGANIZATION AND ARCHITECTURE LTPC